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forgetest: image.health asserts the SDMA clock enable count; the gated engine recorded
The check reads /sys/kernel/debug/clk/sdma/clk_enable_count and fails below 1, naming the fault directly instead of the free-space mismatch it surfaced as after the 150 s settle. BRINGUP item 21 describes the fault and the fix; CAMPAIGN-LOG carries the record of how it was found. Covers: image.health already maps kernel-module-glowforge/** and linux-fslc/**.
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@@ -3879,6 +3879,61 @@ and forgetest all answered on it from a host on a different VLAN, and
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the board reached the IPv6 WAN gateway. IPv6 is on end to end; the
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stale ULA ages out with its own lifetime.
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## 2026-08-24: the SDMA clocks, held by nobody
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The first campaign on dev 20260824201945 (`c-20260824204310-6b6d`) stalled
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on `image.health`: the pre-baseline waited its full 150 s for
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`motion=verified`, which forgectrl never reported, and the test then
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failed on `cnc/free 35618816 exceeds the ring less its 32 KiB gap`. The
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forgectrl log had the shape of it: `liveness probe: ERROR - cannot start
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the probe run` at every controller spawn on every boot since the first
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kernel-trim image (164619), and `MOTION OK` with a healthy p2p on every
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boot before it, the last at 17:47Z on 161618. The kernel log had nothing,
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because the one line that would have said so had been demoted to
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`dev_dbg` the same afternoon on the belief that it was grblHAL's benign
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race.
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The ring's own readbacks named the fault. `cnc/position` read X =
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0x200000 steps on a machine that had not moved (forgectrl showed 39321.60
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mm), the head index sat 2 MiB ahead of the tail on an idle ring, and
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scratch6/7 read back the script's constants (the 0x01ffffff index mask
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and the PWM sample-register address), which is the start of the channel
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context, not its scratch registers. Every context fetch was returning the
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bounce page as last written, not SDMA memory. `/sys/kernel/debug/clk/sdma`
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confirmed it: `clk_enable_count 0`, prepare 1, the engine unclocked.
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The mechanism: imx-sdma enables the engine's `ipg` and `ahb` clocks only
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in `sdma_alloc_chan_resources`, for a dmaengine client, and disables them
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at the end of probe. glowforge.ko takes channel 26 through the SDMA API
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patch's `sdma_get_channel()`, which returned `&sdma->channel[ch]` and
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nothing more. Until the trim, spi-imx on ecspi2 held two SDMA channels
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and so held the clocks; the pulse engine had run on that accident since
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its first image. The round-1 device tree deleted ecspi2's `dmas` on
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purpose (the ring as the only SDMA client), and took the last clock holder
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with it. With the block gated a channel-0 transfer completes at once and
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moves nothing: the script load, the context load, the head sync and the
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position fetch all "succeed"; `cnc/run` sees head == tail right after the
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tail publish and returns -ENODATA; grblHAL treats that as its ordinary
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race and carries on idle; `verify_sdma_script` passes by construction,
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because the write copies the script into the same bounce page the read
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returns. The "47 earlier occurrences" of `cannot start cut; no data
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enqueued` on 164619 and the "no DMA channel held by anyone" observation
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were this fault, read as noise. The SDMA RAM firmware is not involved: it
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never loaded on any image.
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The fix, and what proves it so far: `sdma_get_channel()` enables both
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clocks and a new `sdma_put_channel()` releases them (patch 0003 and the
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API header); the module calls put in remove and in the probe unwind; the
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empty-ring run request logs at ERR level again; `image.health` asserts
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`clk_enable_count >= 1` directly, ahead of the 150 s settle it would
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otherwise wait out. The ecspi2 `dmas` stay deleted. Host-proven: the
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patch round-trips against the kernel tree with 0008 on top, the kernel
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object compiles with no new warnings, the module compiles under `-Werror`
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(its modpost waits on the rebuilt kernel's export), the module's host
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tests and the 270 forgetest tests pass. Owed: the image, then on the
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bench `clk_enable_count` reading 1, `MOTION OK` from the probe,
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`cnc/free` at 33521664 idle, a GRBL job, and the campaign.
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## Superseded status notes
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### Shared machine services — remaining polish, as listed 2026-08-13
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