diff --git a/persistent-memory.d/2026-09-01-ada-inference-server-r750xa.md b/persistent-memory.d/2026-09-01-ada-inference-server-r750xa.md
index d9810c8..7743a4b 100644
--- a/persistent-memory.d/2026-09-01-ada-inference-server-r750xa.md
+++ b/persistent-memory.d/2026-09-01-ada-inference-server-r750xa.md
@@ -148,8 +148,29 @@ Three things decide it, in order:
    entirely. Cleanest harvest: **strip ONE R640 of all 24, use 16, keep 8 as spares**, leaving
    the second R640 whole — rather than half-emptying both into unbalanced populations.
 
+⚠ **"Just move all 768 GB across" is not a shape this board takes.** R640 = 24 slots
+(6 ch/socket x 2 DPC); R750xa = **16 slots (8 ch/socket x 1 DPC)**. 768 GB is either 24x 32 GB
+(more DIMMs than there are slots) or 12x 64 GB (fits, but populates only **6 of 8 channels per
+socket**, leaving ~25% of memory bandwidth unused). The board wants **16 identical DIMMs, 8
+per socket, all channels**. So the real targets are:
+
+    if 32 GB parts   16x 32 =   512 GB     (16 of the 24 in one box)
+    if 64 GB parts   16x 64 = 1,024 GB     (12 from one box + 4 from the other)
+
+**Neither is 768.** And in the 64 GB case the answer is *better* than the question — 1 TB, not
+768 GB, because the two spares hold 24 such DIMMs between them.
+
+⚠ Beyond ~512 GB the return is marginal for this workload (hot set ~150-300 GB; ARC at ~320 GB
+already covers it). Take 1 TB because it is free, not because it is needed. Two costs to weigh
+if it lands there: **64 GB LRDIMMs run hotter** (~6-8 W each vs ~3-5 W, so ~+50 W over the
+32 GB case) in a chassis whose **6 high-performance fans `FD00R` are unaccounted for on the
+invoice** — and this box already sits at ~1 kW on a site where a training run tripped a
+breaker on 2026-08-26.
+
 ⚠ **Confirm the actual DIMM part numbers from iDRAC or the DIMM labels before ordering
-anything.** And confirm the R640s are spares, not in service.
+anything.** R640s confirmed **spares, not in service** (operator, 2026-09-01). **Also add
+DIMM SLOT COUNT to the iDRAC pull** — the 16-slot figure is inferred from the factory CSV
+(qty 16 `M04W6`, "Performance Optimized") and is now load-bearing for a 512-vs-1024 decision.
 
 **Certain (pending the R640 harvest above, which may delete the RAM line):**